The present invention relates to integrated circuits which include sense amplifiers such as used to amplify a small voltage swing signal into a rail-to-rail voltage swing signal.
Frequently, small voltage swing signals need to be amplified into rail-to-rail voltage swing signals when converting analog signals into digital signals as well as when restoring a weak signal used in a digital system to full digital logic levels. A particular type of circuit used to perform such function in a dynamic random access memory (“DRAM”) is known as a sense amplifier. Sense amplifiers are used in both dedicated stand-alone DRAM chips, as well as chips which include an embedded DRAM as a functional element of the chip. Sense amplifiers typically operate by converting a signal representing a charge stored on a storage capacitor of a memory into a rail-to-rail voltage signal.
FIG. 1 is a circuit-level diagram illustrating a sense amplifier 1 according to the prior art, being one such as used to read out a data bit signal from a memory cell of a DRAM or to write a data bit signal to such memory cell. The particular type of sense amplifier depicted therein is one which amplifies a small voltage swing signal between a first bitline (“BLT”) and a second bitline (“BLC”) into a rail-to-rail voltage swing signal between the first and second bitlines. The first bitline BLT carries the signal of interest, such as a signal obtained from a cell of a memory array. The second bitline BLC typically provides a reference signal to the sense amplifier for improved noise immunity. During amplification, the signal level on one of the two bitlines is driven to a predetermined bitline high voltage rail level (“Vblh”) and the signal level on the other one of the two bitlines is driven to a predetermined low voltage rail level such as ground.
Once the signals on the bitlines BLT and BLC have been driven to rail-to-rail levels, they can then be transferred onto “master data” lines MDQT and MDQC when a column select signal (CSL) selects them for reading out of the DRAM. Alternatively, or in addition thereto, the signals on the bitlines BLT, BLC are used to rewrite the amplified rail-to-rail logic level signal to the currently accessed memory cell.
The sense amplifier includes two pairs of cross-coupled devices which operate to drive the signals on the bitlines BLT and BLC to their respective high and low voltage rail levels. A pair of cross-coupled p-type field effect transistors (“PFETs”) P1 and P2 having sources coupled to an internal node X and drains coupled to the bitlines BLT and BLC, respectively, are used to drive one of the bitlines to the high voltage rail level. A pair of cross-coupled n-type field effect transistors (“NFETs”) N1 and N2 having sources coupled to an internal node Y and drains coupled to the bitlines BLT and BLC, respectively, are used to drive the other one of the bitlines to the low voltage rail level. These pairs of cross-coupled PFETs and NFETs require activation at carefully controlled timings in order to avoid amplifying indeterminate signals and the possibility of erroneously inverting the output states of BLT and BLC during amplification. The cross-coupled PFETs P1 and P2 are operated by a device P3 which is connected as a pull-up device to a voltage supply and is operated by a timed signal PSETN. On the other hand, the NFETs are operated by a pull-down network 2 which is timed by a signal SASET. The illustrated pull-down network is referred to as a “sequential pull-down circuit”, having a series of cascaded pairs of transistors and buffers which operate to discharge the voltage at node Y slowly at first, and then accelerate the discharging action as time elapses. In the pull-down network 2, a transistor N5 turns on, then one buffer delay later, a transistor N6 turns on. A buffer delay after transistor N6 turns on, the transistor N7 turns on, finally followed by transistor N8 turning a buffer delay after that. The transistors N5, N6, N7 and N8 have channel widths which progressively increase from the first transistor N5 in the series to the last, in order for these transistors to sink a progressively increasing amount of current as the pull-down network 2 turns on. For example, transistor N5 has width=1, while transistor N6 has width=5, N7 has width=10, and N8 has width=50. The amount of current conducted by each transistor is proportional to its width. When all of the buffer delays have elapsed, all transistors N5 through N8 are turned on, such that the final pull-down current is about 70 times the initial pull-down current when only transistor N5 is turned on.
In an example of operation, prior to a read or write operation, the bitlines BLT and BLC are precharged to a predetermined voltage level referred to as “Vbleq”, which is typically one of ground, Vblh, or an intermediate level between ground and Vblh such as ½ Vblh. The master data lines MDQT and MDQC are precharged to a high potential such as Vblh. When a read operation begins, a small voltage difference signal arises between the signal levels on bitlines BLT and BLC. The timing signal SASET is activated, which causes the PSETN signal to be generated by inverter I1 for operating the pull-up transistor P3. SASET also causes the pull-down network 2 to generate the NSETN drive current to ground to provide the pull-down function.
In such example, it will be assumed that initially BLT is at a higher potential than BLC. When SASET is activated to transition from low logic level to the high logic level, transistor N5 of the pull-down network is activated, causing transistor N2 to conduct and slowly pull down the voltage on BLC to ground. It is important that the pull-down network not discharge the node Y too quickly, otherwise, the signal on the bitline BLT could be pulled low, possibly corrupting the output signal of the data bit sensed by the sense amplifier 1.
The activation of SASET also turns on the pull-up transistor P3. As BLC is slowly pulled towards ground, transistor P1 begins to slowly turn on, causing BLT to be driven towards Vblh. The speed at which BLC is driven lower towards ground is related to the speed at which transistor P1 turns on to drive BLT high. this speed, in turn, is controlled by the amount of current being sunk by the pull-down circuit 2. By virtue of the staged nature of the pull-down circuit, the speed is increased as time elapses so that the value of the data bit is not accidentally flipped when amplification is finished. Once BLT and BLC have stabilized to present a rail-to-rail signal, a column select line CSL can be raised to transfer the signals on BLT and BLC to the master data lines MDQT and MDQC.
A write operation is performed in a manner similar to that of the read operation. At the beginning of the write operation, a data bit signal is transferred from the MDQT and MDQC data lines onto the bitlines BLT and BLC. The SASET signal is asserted and the sense amplifier including the pull-down circuit 2 operate in the same manner as described above to amplify the signals on BLT and BLC to a rail-to-rail signal.
One problem with the above-described circuitry is the large area required by the sequential pull-down circuit 2. Its multiple buffers and multiple transistors of increasing size occupy a large part of the area of a DRAM or embedded DRAM macro. Since many hundreds or thousands of sense amplifiers are needed to support a DRAM array of even modest size, e.g., up to several Mbits, its share of the total area of the DRAM is significant.